A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power

A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power

Spur-reduction techniques for PLLs using sub-sampling phase detection

A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18-μm CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.\u

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the\ud proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 m CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is 80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3 ps rms

DIGITAL RECEIVER PROCESSING TECHNIQUES FOR SPACE VEHICLE DOWNLINK SIGNALS

International Telemetering Conference Proceedings / October 28-31, 1985 / Riviera Hotel, Las Vegas, NevadaDigital processing techniques and related algorithms for receiving and processing space vehicle downlink signals are discussed. The combination of low minimum signal to noise density (C/No), large signal dynamic range, unknown time of arrival, and high space vehicle dynamics that is characteristic of some of these downlink signals results in a difficult acquisition problem. A method for rapid acquisition is described which employs a Fast Fourier Transform (FFT). Also discussed are digital techniques for precise measurement of space vehicle range and range rate using a digitally synthesized number controlled oscillator (NCO).International Foundation for TelemeteringProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit http://www.telemetry.org/index.php/contact-us if you have questions about items in this collection

Low power and low spur sampling PLL

Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced

Spur reduction technique for sampling PLLs

Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced

Phase-locked loop including sampling phase detector and charge pump with pulse width control

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal. \ud \u

PI3K Inhibition Activates SGK1 via a Feedback Loop to Promote Chromatin-Based Regulation of ER-Dependent Gene Expression

Summary: The PI3K pathway integrates extracellular stimuli to phosphorylate effectors such as AKT and serum-and-glucocorticoid-regulated kinase (SGK1). We have previously reported that the PI3K pathway regulates estrogen receptor (ER)-dependent transcription in breast cancer through the phosphorylation of the lysine methyltransferase KMT2D by AKT. Here, we show that PI3Kα inhibition, via a negative-feedback loop, activates SGK1 to promote chromatin-based regulation of ER-dependent transcription. PI3K/AKT inhibitors activate ER, which promotes SGK1 transcription through direct binding to its promoter. Elevated SGK1, in turn, phosphorylates KMT2D, suppressing its function, leading to a loss of methylation of lysine 4 on histone H3 (H3K4) and a repressive chromatin state at ER loci to attenuate ER activity. Thus, SGK1 regulates the chromatin landscape and ER-dependent transcription via the direct phosphorylation of KMT2D. These findings reveal an ER-SGK1-KMT2D signaling circuit aimed to attenuate ER response through a role for SGK1 to program chromatin and ER transcriptional output. : Toska, Castel, et al. show that the PI3K pathway propagates its effects to control chromatin and estrogen receptor (ER) function through SGK1, a PI3K effector. PI3K inhibitors, via a negative-feedback loop, activate SGK1, which phosphorylates the histone lysine methyltransferase KMT2D to attenuate its activity and regulate ER response. Keywords: SGK1, KMT2D, PI3K pathway, estrogen receptor, breast cancer, chromatin regulation, AKT, PI3K inhibitor